LMK05318 Ultra-Low Jitter Single-Channel Network S

By Texas Instruments 143

LMK05318 Ultra-Low Jitter Single-Channel Network S

Texas Instruments' LMK05318 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power-supply noise rejection (PSNR) of the device can reduce bit-error rates (BER) in high-speed serial links.

The device can generate output clocks with 50 fs RMS jitter using TI’s proprietary bulk acoustic wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The digital phase-locked loop (DPLL) supports programmable loop bandwidth for jitter and wander attenuation while the two analog phase-locked loops (APLLs) support fractional frequency translation for flexible clock generation. The synchronization options supported on the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with less than 0.001 ppb (parts per billion) frequency step size for precision clock steering (IEEE 1588 PTP slave). The DPLL can phase-lock to a 1 PPS (pulse per second) reference input and supports optional zero-delay mode on one output to achieve deterministic input-to-output phase alignment with programmable offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.

The device can use a commonly available low-frequency TCXO or OCXO to set the free-run or holdover output frequency stability per synchronization standards. When free-run or holdover frequency stability and wander are not critical, the device can use a standard XO. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmed and can be programmed in-system if needed.

  • One DPLL with:
    • Hitless switching: ±50 ps phase transient
    • Programmable loop bandwidth with fast lock
    • Standards-compliant synchronization and holdover using a low-cost TCXO/OCXO
  • Two APLLs with industry-leading jitter performance
  • Two reference clock inputs:
    • Priority-based input selection
    • Digital holdover on loss of reference
  • EEPROM/ROM for custom clocks on power-up
  • PSNR: -83 dBc (50 mVPP noise on 3.3 V supply)
  • Industrial temperature range: -40°C to +85°C
  • Eight clock outputs with programmable drivers:
    • Up to six different output frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8 V LVCMOS output formats
  • Flexible configuration options:
    • 1 Hz (1 PPS) to 800 MHz on input and output
    • XO/TCXO/OXCO input: 10 MHz to 100 MHz
    • DCO mode: < 0.001 ppb/step for precise clock steering (IEEE 1588 PTP slave)
    • Advanced clock monitoring and status
    • I2C or SPI interface
  • 3.3 V supply with 1.8 V, 2.5 V, or 3.3 V outputs
  • SyncE (G.8262), SONET/SDH (Stratum 3/3E, G.813, GR-1244, GR-253), IEEE 1588 PTP slave clock, or optical transport network (G.709)
  • 400G line cards, fabric cards for Ethernet switches and routers
  • Wireless base station (BTS) and wireless backhaul
  • Test and measurement and medical imaging
  • Jitter-cleaning, wander attenuation, and reference clock generation for 56G/112G PAM-4 PHYs, ASICs, FPGAs, SoCs, and processors