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SN74LV374ADGVRE4

SN74LV374ADGVRE4
Mfr. #:
SN74LV374ADGVRE4
विवरण:
Flip Flops Octal Edge-Trig D-Ty F-F W/3-State Otpt
जीवन चक्र:
यस निर्माताबाट नयाँ।
डाटा पाना:
SN74LV374ADGVRE4 डाटा पाना
डेलिभरी:
DHL FedEx Ups TNT EMS
भुक्तानी:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
थप जानकारी:
SN74LV374ADGVRE4 थप जानकारी SN74LV374ADGVRE4 Product Details
उत्पादन विशेषता
विशेषता मान
निर्माता:
टेक्सास उपकरण
उत्पादन कोटि:
फ्लिप फ्लपहरू
RoHS:
Y
सर्किट संख्या:
8
तर्क परिवार:
74LV
तर्क प्रकार:
D-प्रकार फ्लिप-फ्लप
ध्रुवता:
गैर-उल्टाउने
इनपुट प्रकार:
एकल-समाप्त
आउटपुट प्रकार:
एकल-समाप्त
प्रचार ढिलाइ समय:
19.3 ns
उच्च स्तर आउटपुट वर्तमान:
- 16 mA
निम्न स्तर आउटपुट वर्तमान:
16 mA
आपूर्ति भोल्टेज - न्यूनतम:
2 V
आपूर्ति भोल्टेज - अधिकतम:
5.5 V
न्यूनतम परिचालन तापमान:
- 40 C
अधिकतम परिचालन तापमान:
+ 85 C
माउन्टिङ शैली:
SMD/SMT
प्याकेज / केस:
TVSOP-20
प्याकेजिङ:
रील
समारोह:
D-प्रकार बस इन्टरफेस
उचाइ:
1.05 mm
लम्बाइ:
5 mm
शान्त वर्तमान:
20 uA
चौडाइ:
4.4 mm
ब्रान्ड:
टेक्सास उपकरण
च्यानलहरूको संख्या:
8
इनपुट लाइनहरूको संख्या:
2
आउटपुट लाइनहरूको संख्या:
1
सञ्चालन आपूर्ति भोल्टेज:
2 V to 5.5 V
उत्पादन प्रकार:
फ्लिप फ्लपहरू
कारखाना प्याक मात्रा:
1
उपश्रेणी:
तर्क ICs
एकाइ वजन:
0.002123 oz
Tags
SN74LV374AD, SN74LV374A, SN74LV374, SN74LV37, SN74LV3, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20TVSOP
***ark
Flip-Flop Logic IC; Flip Flop Type:D; Trigger Type:Positive Edge; Output Type:Tri-State Non-Inverted; Supply Voltage Range:2V to 5.5V; Logic Case Style:TVSOP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C ;RoHS Compliant: Yes
***as Instruments
The ’LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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उपलब्धता
स्टक:
Available
अर्डर मा:
3000
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