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SN74ABT853PWRG4

SN74ABT853PWRG4
Mfr. #:
SN74ABT853PWRG4
विवरण:
Bus Transceivers 8 To 9B Parity Bus Transceivers
जीवन चक्र:
यस निर्माताबाट नयाँ।
डाटा पाना:
SN74ABT853PWRG4 डाटा पाना
डेलिभरी:
DHL FedEx Ups TNT EMS
भुक्तानी:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
थप जानकारी:
SN74ABT853PWRG4 थप जानकारी SN74ABT853PWRG4 Product Details
उत्पादन विशेषता
विशेषता मान
निर्माता:
टेक्सास उपकरण
उत्पादन कोटि:
बस ट्रान्ससिभर
RoHS:
Y
तर्क परिवार:
ABT
इनपुट स्तर:
TTL
आउटपुट स्तर:
TTL
आउटपुट प्रकार:
3-State
उच्च स्तर आउटपुट वर्तमान:
- 32 mA
निम्न स्तर आउटपुट वर्तमान:
64 mA
प्रचार ढिलाइ समय:
4.8 ns
आपूर्ति भोल्टेज - अधिकतम:
5.5 V
आपूर्ति भोल्टेज - न्यूनतम:
4.5 V
न्यूनतम परिचालन तापमान:
- 40 C
अधिकतम परिचालन तापमान:
+ 85 C
प्याकेज / केस:
TSSOP-24
प्याकेजिङ:
रील
समारोह:
प्यारिटी परीक्षक संग बस ट्रान्सीभर
उचाइ:
1.15 mm
लम्बाइ:
7.8 mm
सर्किट संख्या:
1
उत्पादन:
BiCMOS
शान्त वर्तमान:
24 mA
प्रविधि:
BiCMOS
चौडाइ:
4.4 mm
ब्रान्ड:
टेक्सास उपकरण
माउन्टिङ शैली:
SMD/SMT
च्यानलहरूको संख्या:
8
हालको आपूर्ति - अधिकतम:
38 mA
सञ्चालन आपूर्ति भोल्टेज:
5 V
ध्रुवता:
गैर-उल्टाउने
उत्पादन प्रकार:
बस ट्रान्ससिभर
कारखाना प्याक मात्रा:
1
उपश्रेणी:
तर्क ICs
एकाइ वजन:
0.003175 oz
Tags
SN74ABT853PWR, SN74ABT853P, SN74ABT853, SN74ABT85, SN74ABT8, SN74AB, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INV 24TSSOP
***as Instruments
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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उपलब्धता
स्टक:
Available
अर्डर मा:
3500
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